The present invention relates to a variable-length encoding and decoding apparatus for encoding or decoding an image compression bit stream according to the MPEG standard.
In the image compression bit stream according to the MPEG standard (the details which are described in xe2x80x9cTextbook of Recent MPEGxe2x80x9d (ASCII) edited by Hiroshi Fujiwara, xe2x80x9cAll of MPEG-4xe2x80x9d (Kogyo chosakai) written and edited by Sukeichi Miki, and the like are avoided), in order to identify a start position of information such as a screen and a type of data included in the bit stream after the start position, a fixed length code having a specific bit pattern (hereinafter, referred to as a start code) is inserted. When compressed image information is decoded, this start code is detected, and decoding processing is performed on the basis of the following information (hereinafter, referred to as xe2x80x9cstart code valuexe2x80x9d). In a structure of the start code, as shown in FIG. 7(a), an 8-bit start code value is added to 23 pieces of xe2x80x9c0xe2x80x9d and a single piece of xe2x80x9c1xe2x80x9d, 24 bits in total. Taking MPEG4 (Moving Picture Experts Group 4) as an example, the standardized start codes are as shown in FIG. 7(b).
The following measure is taken so as to enable to clearly distinguish the start codes from the other data. Bit patterns which are difficult to appear in the other data are adopted. Further, in the process of encoding the image information, the same bit pattern as that of the start code sometimes results in depending on the combination of the code words. However, in order to avoid an emulation due thereto, in an encoder, a 1-bit bit stream is inserted in the code word which has possibility to be emulated. Further, synchronizing words such as a start code and a sync marker are arranged such that each distance between the heads of synchronizing words becomes a positive integral multiplication of 8 as shown in FIG. 6.
When a conventional code detecting apparatus detects the synchronizing words as described above, the apparatus detects whether a bit stream having a certain bit length coincides with a pattern of the synchronizing word employing a shift register of 1 bit/cycle or 8 bits/cycle, for example, whether the bit sequence of 32 bits from the head of a shift register coincides with the pattern of the synchronizing word.
There is a case where an overlap is generated between image compression information (fixed length code, variable-length code) in the bit stream and the synchronizing word due to transmission errors and the like coming from the worsening of a communication state.
As an example, a state where the overlap is generated between a variable-length code and the synchronizing word will be described with reference to the drawings. Initially, FIG. 4(a) shows a normal bit stream in which the overlap is not generated. A 32-bit synchronizing word 501 follows a variable-length code 500. On the other hand, FIG. 4(b) shows a bit stream in which the overlap is generated. The 3-bit data from the least significant bit of a variable-length code 510 and 3 bits from the most significant bit of the following 32-bit synchronizing word 511 overlap with each other. The state as shown in FIG. 4(b) is detected, and further the synchronizing word following the variable-length code is detected, resulting in an efficiency improvement of an image decoding processing and suppressing an image deterioration of a decoded image.
However, in the conventional synchronizing word detecting apparatuses, there are some in which the synchronizing word cannot be detected when the overlap is generated between the bit stream and the synchronizing word in the image compression information (fixed length code, variable-length code). In addition, there are some in which even if the synchronizing word can be detected, the state where the image compression information and the synchronizing word overlap with each other cannot be detected.
The synchronizing word is important information which shows the following image decoding processing. Therefore, non-detection or erroneous detection of the synchronizing word has a strong possibility of affecting the following image decoding processing, and causes an efficiency lowering of the image decoding processing and deteriorating the quality of the decoded image. In addition, such an error that the variable-length code and the synchronizing word overlap with each other cannot be detected. Therefore, there is a case where, when, actually, the image decoding processing should be interrupted immediately after error detection, the processing is kept as it is, thereby generating an erroneous decoded image and deteriorating the quality of an output image.
Furthermore, in the conventional synchronizing word detecting apparatus, searching for the synchronizing word is performed with the data being abandoned, and the above-described processing is kept until the synchronizing word is detected. Therefore, it is impossible for the apparatus to identify whether the synchronizing word exists in the most neighboring byte align point.
The present invention is made to solve the above-described problems, and it has for its object to provide a variable-length encoding and decoding apparatus which, when the overlap is generated in the image compression information and the synchronizing word, can detect the synchronizing word and can detect an error that the image compression information and the synchronizing word overlap with each other, and further can efficiently identify the presence of the synchronizing word in the most neighboring byte align point.
In order to solve the problems, according to a 1st aspect of the present invention, there is provided a variable-length encoding and decoding apparatus comprising: a register which stores a bit stream of video compression information from an external apparatus; a first shift register which shifts a signal to the high-order direction by n bytes per a machine cycle; first selection means for selecting a vacant section of a successive predetermined bit number in a predetermined section from the least significant bit of the first shift register, and successively storing a signal of the first shift register from the high-order side of the vacant section of the first shift register; a second shift register which shifts the signal to the high-order direction by the optional bit number per a machine cycle; second selection means for selecting a vacant section of the successive predetermined bit number in a predetermined section from the least significant bit of the second shift register, and successively storing a signal of the second shift register from the high-order side of the vacant section of the second shift register; third selection means for selecting a signal of the successive predetermined bit number in the second shift register; variable-length encoding and decoding means for performing decoding and simultaneously outputting code length information which shows a code length of a variable-length code in the case where a signal selected by the third selection means is a variable-length code and can be decoded; fourth selection means for selecting a signal of the successive predetermined bit number from the first shift register to output the same while decoding processing of the variable-length code is performed by the variable-length encoding and decoding means, and outputting a signal input from the third selection means when the decoding processing is completed; synchronizing word detecting means having first code detecting means for comparing the signal of the first shift register selected by the fourth selection means with a specific bit pattern to perform coincidence detection, and second code detecting means for comparing the signal of the second shift register selected by the fourth selection means with the specific bit pattern to perform coincidence detection; specific bit pattern position information management means which, when a signal of the specific bit pattern in the first shift register is detected by the first code detecting means and a signal of the most significant bit of the specific bit code is moved to the second shift register, sets a head bit position information of the specific bit pattern in the second shift register at that timing, and, when shift processing is generated in the second shift register, updates the head bit position information in accordance with the shift amount; overlap detecting means which judges whether or not an overlap is generated between the variable-length code and the specific bit pattern in the second shift register, on the basis of code length information of the variable-length code from the variable-length encoding and decoding means and the head bit position information of the specific bit pattern from the specific bit pattern position information management means and, when the overlap is detected, outputs an overlap notifying signal.
Thereby, the overlap can be detected with high precision, and the quality of the decoded image from image compression information can be enhanced.
According to a 2nd aspect of the present invention, in the variable-length encoding and decoding apparatus of the 1st aspect, the specific bit pattern position information management means comprises a plurality of storage means for storing each head bit position information of plural specific bit patterns in the second shift register, and the overlap detecting means judges whether or not the overlap of the variable-length code and the specific bit pattern is generated in the second shift register by using the head bit position information closest to the most significant bit or all the head bit position information of the second shift register among the plurality of the head bit position information stored in the plurality of the storage means.
Thereby, even when the head bits of two synchronizing words exist in the second shift register, the overlap between both the two synchronizing words and the variable-length code can be detected.
According to a 3rd aspect of the present invention, in the variable-length encoding and decoding apparatus of the 2nd aspect, the specific bit pattern position information management means initializes the head bit position information of the plurality of the storage means in the case where the head of the specific bit pattern does not exist in the second shift register, and, each time when the signal of the specific bit pattern is detected by the first code detecting means, selects one in which the head bit position information has an initial value among the plurality of the storage means thereby to set the head bit position information.
Thereby, overwriting in the head bit position information which is already stored in any of the storage means when the synchronizing word is detected can be avoided.
According to a 4th aspect of the present invention, in the variable-length encoding and decoding apparatus of any of the 1st through 3rd aspects, when the corresponding code does not exist in a lookup table of the variable-length code while the variable-length encoding and decoding means decodes the variable-length code signal selected by the third selection means, the variable-length encoding and decoding means outputs a maximum code length of the variable-length code in the lookup table to the overlap detecting means.
Thereby, even when an error is generated in decoding processing of the variable-length code, the overlap of the synchronizing word and the variable-length code can be detected, and the overlap detection with high precision can be realized.
According to a 5th aspect of the present invention, in the variable-length encoding and decoding apparatus of any of the 1st through 3rd aspects, when the corresponding code does not exist in the lookup table of the variable-length code while the variable-length encoding and decoding means decodes the variable-length code signal selected by the third selection means, the variable-length encoding and decoding means outputs a value which is obtained by adding 1 to the number of bits which coincides successively from the respective most significant bits in the selected variable-length code and the variable-length code in the lookup table to the overlap detecting means.
Thereby, even when an error is generated in decoding processing of the variable-length code, the overlap of the synchronizing word and the variable-length code can be prevented from being erroneously detected, and the overlap detection with higher precision can be realized.
According to a 6th aspect of the present invention, the variable-length encoding and decoding apparatus of any of the 1st through 5th aspects comprises: byte align point management means which, when the specific bit pattern in the second shift register is detected by the second code detecting means, at that timing, initializes a byte align point of the bit stream and, when shift processing is generated in the second shift register, updates the byte align point in accordance with the shift amount.
Thereby, the data is shifted by the second shift register at the time when the next synchronizing word is searched so that the byte align point becomes the most significant bit, thereby detecting the synchronizing word by the second code detecting means, and the erroneous detection due to such as the emulation of the synchronizing word can be prevented.
According to a 7th aspect of the present invention, the variable-length encoding and decoding apparatus of any of the 1st through 6th aspects comprises: second synchronizing word detecting means which regards the most neighboring byte align point from the most significant bit of the second shift register as a reference point, in accordance with byte align point information of the byte align point management means, and compares the signal of the successive predetermined bit number with the specific bit pattern thereby to perform coincidence detection.
Thereby, the detection of the synchronizing word can be performed for each byte align point, and efficient synchronizing word detection and image decoding processing can be performed.